1. Field of the Invention
The present invention relates to X-ray detectors. More particularly, it relates to Thin Film Transistor (TFT) array substrates for use in X-ray detectors.
2. Description of Related Art
A widely used method of medical diagnosis is the X-ray film. As such films produce photographic images, time consuming film-processing procedures are required to obtain the results. However, digital X-ray sensing devices (referred to hereinafter as X-ray detectors) that employing thin film transistors have been recently developed. Such X-ray sensing devices have the advantage of providing real time diagnosis.
FIG. 1 is a cross-sectional view illustrating one pixel of an array substrate of a conventional X-ray sensing device. That X-ray sensing device includes a Thin Film Transistor (TFT) “T” on a substrate 1, a photoconductive film 2, and various conductive elements that are described subsequently. Also included, but not shown in FIG. 1, are a scanning integrated circuit and a data integrated circuit.
Referring to FIG. 1, the photoconductive film 2 produces electron-hole pairs 6 in proportion to the strength of external radiation. Thus, the photoconductive film 2 acts as a photoelectric transducer that converts incident X-rays into electron-hole pairs 6. An external voltage Ev is applied across a conductive electrode 7 and a pixel electrode 62. That voltage causes the electron-hole pairs 6 in the photoconductive film 2 to separate such that X-ray induced electrical charges accumulate in the pixel electrode 62. Those electrical charges are applied to a second capacitor electrode 60, and are consequently stored in a storage capacitor “S” formed by the second capacitor electrode 60 and a first capacitor electrode 58 that is formed over a ground line 42. The pixel electrode 62, the first capacitor electrode 58 and the second capacitor electrode 60 are beneficially comprised of a transparent conductive material such as Indium-Tin-Oxide (ITO) or Indium-Zinc-Oxide (IZO). Furthermore, an insulating dielectric layer 15 is interposed between the first capacitor electrode 58 and the second electrode 60. That dielectric layer is beneficially comprised of Silicon Nitride (SiNx).
Still referring to FIG. 1, the TFT “T” connects to the storage capacitor “S” such that electrical charges accumulated on the storage capacitor “S” can flow through the TFT “T” and into the data integrated circuit (not shown) when the TFT “T” is turned ON by the scanning integrated circuit (not shown).
FIG. 2 is a plan view illustrating several pixels of an array substrate for an X-ray sensing device according to the conventional art. Gate lines 50 are arranged in a transverse direction and data lines 53 are arranged in a longitudinal direction. Gate pads 87 are formed at each end of each gate line 50. Those gate pads are associated with gate pad contact holes 96. The gate pads formed at one end of the gate line are cut off during a subsequently process of bonding two substrates to form a large substrate, following a short/open-circuit test. The cutting portion, called a tiling portion “A,” is used for tiling array substrates to form a large-sized X-ray image detector. External drive circuitry (not shown) connects to the other gate pads 87 through the gate pad contact holes 96 using a Wire Bonding method. The gate pads 87 also connect to a gate shorting bar that makes the gate pads have equipotentials. The shorting bar is used during the short/open-circuit testing.
A TFT “T” is formed near each crossing of the gate and data lines 50 and 53 (for simplicity only one TFT “T” is shown in detail in FIG. 2). Each TFT acts as a switching element. A ground line 42 is arranged perpendicular to the gate lines 50. The ground line 42 acts as a common line for the neighboring pixels.
A first capacitor electrode 58 and a second capacitor electrode 60 of a storage capacitor “S” are located in each pixel area, with the pixel areas being the regions between the gate lines and the data lines. Additionally, as shown in FIG. 1 but not shown in FIG. 2, a dielectric layer 15 of Silicon Nitride (SiNx) is interposed between first capacitor electrodes 58 and the second capacitor electrodes 60. Pixel electrodes 62 that extend over the TFTs “T” are then located in the pixel areas. Although not shown in FIG. 2, but as shown in FIG. 1, in order to store the holes which are generated in the photoconductive film 2, each pixel electrode 62 electrically connects to the second capacitor electrode 60 of that pixel. Furthermore, each pixel electrode 62 is electrically connected to a drain electrode 33 of that pixel's TFT “T” via a drain contact hole 85.
The fabrication steps of the array substrate illustrated in FIG. 2 will be explained with reference to FIGS. 3A to 3E, which are cross-sectional views taken along lines I—I, II—II and III—III.
Referring to FIG. 3A, a first metal layer is formed on a substrate 71 by depositing a metallic material such as Aluminum (Al), Al-alloy, Molybdenum (Mo), Tantalum (Ta), Tungsten (W) or Antimony (Sb). A gate line 50, a gate electrode 73 that extends from the gate line 50, and a gate pad (not shown) on each end of the gate line 50 are then formed by patterning the first metal layer. Simultaneously formed are a shorting bar (not shown) and a shorting bar connector (also not shown) that connects the gate pads to the shorting bar. Then, a first insulation layer 75 is deposited over the substrate 71 and over the first metal layer. The first insulation layer 75 can be comprised of an inorganic substance, such as silicon Nitride (SiNx) or Silicon Oxide (SiOx), or of an organic substance such as BCB (Benzocyclobutene) or an acryl. Silicon Nitride (SiNx) is assumed to be employed hereinafter.
As shown in FIG. 3B, a pure amorphous silicon (a-Si:H) layer and a doped amorphous silicon (n+ a-Si:H) layer are sequentially formed over the first insulation layer 75. Those silicon layers are then patterned to form an active layer 86 and an ohmic contact layer 91. CVD (Chemical Vapor Deposition) or the Ion Injection Method is beneficially used to form the doped amorphous silicon layer.
Referring now to FIG. 3C, a source electrode 32, a drain electrode 33, and a ground line 42 are then formed. First, a second conductive metal layer of Aluminum (Al), Al-alloy, Molybdenum (Mo), Tantalum (Ta), Tungsten (W) or Antimony (Sb) is deposited. The second conductive metal layer is then patterned to form the source electrode 32, which extends from the data line (reference element 53 of FIG. 2) over the gate electrode 73; the drain electrode 33, which is spaced apart from the source electrode 32 and over the gate electrode 73; and the ground line 42, which crosses under the storage capacitor “S” (see FIG. 2). A portion of the ohmic contact layer 91 on the active layer 86 is then etched to form a channel region using the source and drain electrodes 32 and 33 as masks. Thus, the TFT “T” (see FIG. 2) is complete.
Next, the first capacitor electrode 58 is formed over the ground line 42 by depositing and patterning a transparent conductive material such as Indium-Tin-Oxide (ITO) or Indium-Zinc-Oxide (IZO). The first capacitor electrode 58 is in electrical contact with the ground line 42. A dielectric protection layer 81 is then formed over the TFT, over the first capacitor electrode 58, and over the first insulation layer 75 by depositing Silicon Nitride (SiNx). Thus, the first insulation layer 75 and the protection layer 81 are stacked over the gate pad (see FIG. 2) and over the gate line 50. A second capacitor electrode 60, which corresponds in size to the first capacitor electrode 58, is then formed on the protection layer 81 and over the first capacitor electrode 58. The second capacitor electrode 60 is beneficially comprised of Indium-Tin-Oxide (ITO) or of Indium-Zinc-Oxide (IZO).
As shown in FIG. 3D, a second insulation layer 83 is then formed, beneficially by depositing an organic substance such as BCB (Benzocyclobutene). BCB is a good choice because it has a low dielectric permittivity. After that, the second insulation layer 83 and the protection layer 81 are etched to form a drain contact hole 85 over the drain electrode 33. Simultaneously, a capacitor electrode contact hole 95 is formed by etching the second insulation layer 83 over the second capacitor electrode 60. Also simultaneously, by etching the second insulation layer 83, the protection layer 81, and the first insulation layer 75, a cutting furrow 99 to the tiling portion “A” (see FIG. 2) and a gate pad contact hole (see element 96 of FIG. 2) over the gate pad (see element 87 of FIG. 2) are formed. As described above, the cutting portion of the gate line 50, i.e., the tiling portion “A,” is cut after the panel is completed. The cutting portion is utilized for tiling substrates to form a large-sized X-ray detector.
Referring now to FIG. 3E, a pixel electrode 62, which connects to the drain electrode 33 via the drain contact hole 85 and to the first capacitor electrode 60 via the capacitor electrode contact hole 95, is formed by depositing and patterning a transparent conductive material such as ITO or IZO. However, the transparent conductive material deposited on the cutting furrow 99 and on the gate pad contact hole (not shown) should be removed. Since the pixel electrode 62 is conductive, the pixel electrode 62 and the second capacitor electrode 60 have an equipotential.
Referring now back to FIG. 3D, as noted, the drain contact hole 85 is formed by etching the second insulation layer 83 and the protection layer 81, the capacitor electrode contact hole 95 is formed by etching the second insulation layer 83, and the cutting furrow 99 is formed by etching the second insulation layer 83, the protection layer 81 and the first insulation layer 75. Further, all those openings are all etched at the same time. However, when etching the different layers (the first insulation layer 75, the protection layer 81 and the second insulation layer 83) it is difficult to accurately control the etching process.
When dry etching, the etching process is controlled by monitoring a gas that is produced by a chemical reaction between the etching gas and the insulation or protection layers using an electrical device, referred to as an EPD (end point detector). The EPD converts the amount of the produced gas to an electrical voltage. Thus, the duration of the etching can be controlled based upon the electrical voltage. However, it is difficult to detect the gas that is produced while etching only the drain contact hole 85 and the capacitor electrode contact hole 95 because the amount of gas that is produced is so small. Thus, it is beneficial to enlarge the etching area by also etching the cutting furrow 99. This produces more gas, which improves the operation of the EPD.
However, some problems occur in the above-mentioned process. Note that three layers need to be etched when forming the cutting furrow and the gate pad contact hole, only one layer needs to be etched for the capacitor electrode contact hole, and only two layers need to be etched for the drain contact hole. When forming the cutting furrow and the gate pad contact hole using the dry etching method, the other contact holes are over-etched due to the fact that the protection layer and the insulation layers do not have etching selectivity with each other. Thus, the drain electrode and/or the second capacitor electrode can be deteriorated by over-etching, with the result being a possible manufacturing defect in the array substrate.